AMD details Zen 3 and Zen 4 Based Epyc- New Socket in Tow
AMD has spilled the beans in the recently held HPC AI Advisory conference in UK. We have already known that AMD is working on next-gen Zen cores, roadman already shows plans till zen 5. But this is the first time we have few more details about Zen 4 and 5 other than just code name.
Zen 3 – Epyc Milan
Epyc Milan is the processor that has stolen the limelight even before release. That’s because the world’s fastest exascale computer is being built using this CPU. This even beats the pace of Intel’s first exascale supercomputer.
Epyc Milan won’t scale the next fabrication process as we have already known that zen 3 will use 7nm+ process technology from TSMC. It will keep pin compatibility with existing motherboard i.e. no new socket will be introduced and existing customers can just swap in CPUs in. PCIe 4 support is given. DDR 4 Memory will be there too. While it is sad that it will be 7nm product again, AMD has shown slide where Milan seems to perform better than its rival. (Rival? who could it be? :P). The biggest change is regarding L3 cache. Currently AMD deploys 16MB L3 cache per CCX (Computer complex which houses a group of CPU). Zen 3 will have 32 MB L3 cache per die. Thus all cores will share the same L3 cache instead of some cores sharing one small cache etc.
Zen 4 – Epyc Genoa
This is the brand new cores that have little to no information until today which will bring new features and process technology.
The new CPU will require a new socket, DDR5 will be a supported memory technology. Although not explicitly shared but PCIe 5.0 is also on the cards. Also, this will use next gen fabrication process most probably at 5nm.
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